Ms. Payal Jangra

Ms. Payal Jangra received her Bachelor of Technology degree in Electronics and Communication Engineering from Deenbandhu Chhotu Ram University of Science and Technology (DCRUST), Murthal, Haryana, India, in 2015. She completed her M.Tech in Electronics and Communication Engineering (VLSI Design) from the same university in 2017 with a CGPA of 8.2. She has submitted her Ph.D. thesis in Electronics Engineering at DCRUST, Murthal, with the research title “Spintronics Based In-Memory Computation”. Her doctoral research focuses on the design and performance optimization of emerging spintronic memory devices, including STT-MRAM, SOT-MRAM, VCMA-MRAM, and VGSOT-MRAM, for logic and in-memory computing applications using Cadence Virtuoso. She has designed and implemented energy-efficient logic, combinational circuits, and in-memory computing architectures, analyzing key performance parameters such as latency, power, and energy consumption. Ms. Payal Jangra has actively contributed to teaching and academic development as a Teaching Assistant during her M.Tech and Ph.D. programs, assisting in laboratory sessions, tutorials, and postgraduate project supervision in VLSI Design and Digital Electronics. She has published multiple research articles in SCI, ESCI, and Scopus-indexed journals and conferences, with a strong research orientation toward energy-efficient computing and emerging memory technologies.